Add Verilog files recursively in Altera Quartus II

This post describes how you add multiple Verilog files recursively to your project in Altera Quartus II. If you are using VHDL you can simply change the file matching from "*.v" to "*.vhd*".

Create a file named "addallv.tcl" in your project folder with the contents listed below. Change "myfolder" to the name of the sub-folder below your project folder that contains the files (or folders with files) you would like to add. Run it in the Tcl Console with:

source addallv.tcl

addall.tcl:

package require ::quartus::project
package require fileutil
#addallv.tcl by http://www.thalin.se

set folderName "myfolder"

foreach file [fileutil::findByPattern $folderName *.v] {
    puts $file
    set_global_assignment -name VERILOG_FILE $file
}

Hints

You have to enable the the Tcl Console by selecting View -> Utility Windows -> Tcl Console.

Run the command by typing it in front of tcl> and press return.